1. Field of the Invention
The present invention relates to a Thin Film Transistor (TFT), a method of manufacturing the TFT, and a flat panel display including the TFT and its method of manufacture. More particularly, the present invention relates to a TFT having an improved structure including an InterLevel Dielectric (ILD) layer and source/drain electrodes, and a method of manufacturing the TFT, and a flat panel display device including the TFT.
2. Description of the Related Art
A flat panel display device such as a liquid crystal display (LCD), an organic light-emitting diode (OLED), or an inorganic light-emitting diode is categorized by driving methods into a passive matrix (PM) flat panel display device using a passive driving method and an active matrix (AM) flat panel display device using an active driving method.
In the PM flat panel display device, anodes and cathodes, respectively, are arranged in a plurality of columns and rows, and a scanning signal is supplied by a row driving circuit to the cathodes. In this case, only one row of the plurality of rows is selected. In addition, a data signal is input by a column driving circuit into each pixel.
The AM flat panel display device is widely used as a display device, which controls a signal input into each pixel using a thin film transistor (TFT) and is adapted to processing of an enormous amount of signals to realize a moving image.
In a TFT of a flat panel display, an active layer comprised of a semiconductor is formed on a substrate. A gate insulating layer is formed on the active layer to cover the active layer. A gate electrode 40 formed on the gate insulating layer. The gate electrode is covered with an InterLevel Dielectric (ILD) layer, and contact holes through which source/drain regions of the active layer are exposed are formed in the gate insulating layer and the ILD layer. Source/drain electrodes are formed on the ILD layer. The source/drain electrodes are connected to the source/drain regions of the active layer through the contact holes. When forming the source/drain electrodes, a variety of signal interconnections of the flat panel display can be formed together.
The source/drain electrodes and the signal interconnections can be formed of molybdenum or molybdenum alloy. Since molybdenum has a high specific resistance, the resistance of the source/drain electrodes and the signal interconnection is increased, resulting in a signal delay in a flat panel display including the TFT. This signal delay causes the lowering of the picture quality of the flat panel display.
In order to solve these problems, the source/drain electrodes and the signal interconnection have been formed of a double layer comprising a molybdenum layer and an aluminum layer having a low resistance formed on the molybdenum layer. However, one of the source/drain electrodes is in contact with an Indium Tin Oxide (ITO) layer of a pixel electrode (not shown). Since an oxide layer is formed between the aluminum layer and the ITO layer, the contact resistance between the pixel electrode and the source/drain electrodes contacting the pixel electrode is increased.